ISLPED’07 Summary

Once again the International Symposium on Low Power Electronics and Design has delivered an impressive technical program which featured several invited talks from leaders in the field along with a special embedded tutorial on ultra low power digital techniques.
     The first talk was delivered by Rober Chau, who is an Intel Senior Fellow and director of transistor research and nanotechnology in Intel’s Technology and Manufacturing Group. He holds over 125 U.S patents and is a leader in research efforts in emerging nanotechnologies for future nanoelectronics applications. His talk titled, “Nanotechnology for Low-Power and High-Speed Nanoelectronics Applications” had many interesting insights into the future including the fact that more and more non-silicon materials will be used to enhance speed and reduce vertical leakage in transistors. His talk was nicely followed by a paper on “Compact Modeling of Carbon Nanotube Transistor for Early Stage Process-Design Exploration”.
     A more entertaining special session on the future of on-chip interconnection architectures was given by Shekhar Borkar (Intel) and William Dally (Stanford University). The two experts had very fundamental arguments regarding interconnects which at one point came to a discussion about the definition of a data bus. Borkar takes a simple approach to the future of on- chip interconnects saying that they should basically be made as bus lines and this would be the most efficient and simple solution to multi-cores. On the other hand Dally argues that this is an old school approach that should have died a long time ago, and that mesh networks are the way to go to solve the problem efficiently. Both cases had very good points which I think could be combined to make the optimal processor.
     Next a Berkeley View on the “Parallel Computing Landscape” was given by David Patterson. His talk included some research which reviled some possible applications that are in store for parallel computing, this is very important because you cannot make an efficient design without understanding exactly how and what it will be used for. David Patterson said that this is one of the most interesting times in technology, and that the parallel computing problem is a huge obstacle especially for software engineers. Although David was optimistic with what’s coming up with parallel computing some believe that this new multi-core programmability challenge will be the end to Moore’s Law.
The final Plenary Speech was given by Google’s Luiz Barroso and was entitled All Watts Considered. The main ideas that were presented were with the way one should look at power provisions and energy efficiency for large data-centers. The approach taken by Luiz is that the whole building that is the data-center should be considered as a low power computer which Luiz jokingly referred to as a “landheld” low power device. The main power savings do not come from looking at each server individually or even the components within them, but to look at the whole network and be able to shift the activity periods to operate at optimal efficiency as a group. Luiz also added some slides about using efficient power supplies. You can read some of the interesting publications on Luiz’s home page.
     On top of these special sessions the Symposium was packed with leading edge papers on electronics and low power design. Some papers presented some very usual techniques to optimize for power which I will blog about in the near future. The paper that I found to be most innovative and happened to win one of the Best Paper Awards was titled “Vibration Energy Scavenging and Management for Ultra Low Power Applications”. This paper gives a solution to remote ultra low power applications, and a very optimistic outlook on the future of ultra low power design and energy harvesting.


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