Passive Voltage Scaling for Ultra Low Power Microcontrollers

An interesting low power design technique has been presented by Youngjin Cho, Younghyun Kim and Naehyuck Cang from Seoul National University. Their paper titled “PVS: Passive Voltage Scaling for Wireless Sensor Networks” describes a way to gain 34% more network lifetime and 26% shorter average latency over modern wireless sensor networks. This technique is ideal for mid to high performance ultra low power microcontrollers like the TI MSP430. A common high-level low power technique applied to embedded systems is called Dynamic Voltage Scaling (DVS). However for the mid to high performance embedded systems DVS is generally not applicable due to the cost and area overhead associated with the addition of the required DC/DC converter. Moreover, these embedded systems usually have extremely light current consumption making the DC/DC converter operate in a very inefficient region. This usually means that the power savings from DVS are offset by the power losses in the DC/DC converter. The new PVS technique monitors battery voltage with an embedded voltage supervisor and sets the highest safe clock frequency using an internal Phase Lock Loop (PPL), or Delay Lock Loop (DLL). This allows for the maximum microcontroller performance that is achievable at the given battery voltage level. Also, this eliminates the need for a DC/DC converter altougether. This technique is especially useful for systems powered by supplies with steep discharge characteristics, like alkaline batteries. Unlike DVS, PVS dose not aim to achieve the most power efficient operation out of the microcontroller, however it aims to minimize the power losses from power delivery systems, peripherals, and the specific battery chemistry. Ultimately, the overall battery lifetime is increased. This technique has been implemented by the authors of the paper on a wireless sensor network based on the MSP430F1611. The results demonstrate a 64% and 34% improvement in battery lifetime and 3% and 26% improvement in average latency over a traditional wireless sensor network with a DC/DC converter and a fixed clock frequency, and a modern configuration with a DC/DC converter and a fixed clock frequency, respectively. These are extremely impressive results, however they might be somewhat different based on the DC/DC converter that was used. If the converter was high efficiency, specifically designed for low current applications, maybe the results would not be so dramatic. Nevertheless in my opinion this is still a very innovative low power design technique.

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