Lowering Power in your Logic

If your design has the right condition, a multiple Vdd design could save you a bunch in power consumption. The basic idea behind having multiple power supplies is to lower the operating voltage of appropriate logic gates which naturally will cut down on the power dissipation through those gates. The gates that operate from the lower voltage pay the price of becoming slower. So the trick is to find the appropriate logic paths in your design that are not time constrained. For example if you have two logic paths operating simultaneously one consisting of 4 gates and the other of 8 and the result of both is needed to continue operations, the path with 4 gates is a perfect candidate for scaling its voltage. You can lower that path’s voltage supply effectively slowing it down, which in this case does not make a difference in the overall design since the outcome of the 8 gate path has to be processed anyway. There are many reasons for not slowing the whole logic system down but one to consider is that in most (not all) cases it is good to get things done quickly and go back to sleep or low power mode. Since we can not slow down the whole system there is a need for multiple power supplies. There are however overheads with this, for instance you will need level shifters when two different voltage level logic paths converge into a new logic function, and obviously there are costs in designing two different power supplies. However if power consumption is the underlining design specification, this technique can help.

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