Archive for the ‘Research’ category

Design MSP430 Ultra-Low Power Challenge – $10,000 In Prizes

October 28, 2009

Hello everyone, there is an exciting low power design competition put on by Texas Instruments. You can win cash and TI development tools. I personally think that the MSP430 is a smart choice for any embedded design especially one that prioritizes battery life. I like working with the MSP430 and there is a lot of help from TI and from other online communities so even if you are not familiar with it don’t hesitate to start.  It’s going to be interesting to see all the creative designs and see how low the power consumption can get.

The contest information is below:

Show us what you’re made of by submitting your MSP430 eZ Designs and learning from other MSP430 users around the world. Choose from your favorite ultra-low power devices and tools – MSP430×1xx, MSP430F2xx, MSP430×4xx, MSP430F5xx, CC430Fxxxx. Submit your design in the MSP430 forum and learn more about the world’s lowest power MCU.

Get your free silicon samples at
Get your discounted development tools and software at, and save through January 19, 2010:
• Get a 25% tool discount on any MSP430 development tool through Avnet.
• Get a 50% discount of the Code Composer Studio v4 software (a $500 value) through Avnet.

TI Microcontrollers on Facebook:


30 Picowatt Sleep Mode Microchip

January 16, 2009

The Phoenix Processor developed by researchers at the University of Michigan can run on a watch battery for 263 years. The processor uses 10 times less power than comparable chips when active and 30,000 times less power in sleep mode. The processor is designed for sensor-based devices. Some applications include medical implants, environment monitors, structural integrity of buildings and bridges. The overall design was based around reducing sleep mode power consumption since in most application the sensor is a sleep 99 percent of the time. The processor runs on 0.5 Volts and in sleep mode consumes 30 picowatts. This is a very exciting development, which could open up the door for electronics to be used in applications that are currently purely mechanical due to the inconvenience of replacing batteries.

For more info: Phoenix Processor

Memristors could help create more power efficient electronics

May 1, 2008

Researchers at HP Labs have demonstrated the existence of a fourth basic element in integrated circuits know as a memristor. Systems utilizing the memristor’s capability of memory retention without power could make it possible to develop far more energy-efficient computing systems. Memristor-based computers would not require the energy consumptive process of booting up, instead they would turn on instantly using less power and possibly increasing system resiliency and reliability. They would be perfect for applications that require a lot of memory without a lot of battery-power drain. A mathematical model and a physical example that prove the memristor’s existence appear in a paper published in the April 30 issue of the journal Nature.

Short Video on the memristor

Low Power Design Symposiums 2008

January 21, 2008

I attended the ISLPED Low Power Electronics and Design symposium in 2007 and found it to be excellent. There were a lot of interesting papers presented and I did learn a few low power design techniques that I since applied in my own designs. This year the symposium is being held in Bangalore, India sometime in early August. There is a WikiCFP up design to organize the calls for papers. Also the NanoPower Forum will be held in Irvine, California from June 2nd – 4th. The primary focus of the forum is around “ultra low power” electronics. What I find most interesting is the talks and papers on energy harvesting techniques and applications. I think this will be a great event, so if you’re interested in the low power world, make sure to keep those days open.


NanoPower Forum

10 times more charge for lithium-ion batteries

January 17, 2008

A group or researchers have formulated a way of increasing the capacity of lithium-ion batteries. The team lead by Yi Cui at Stanford University, has build a substrate out of silicon nanowiers capable of holding ten times more lithium compared to a carbon solution. Ten times more lithium means 10 times more charge. The findings are discussed in a paper published in Nature Nanotechnology on December 16th titled “High-performance lithium battery anodes using silicon nanowires.” This new technology is exciting because not only could it be applied to consumer electronics, but more importantly in applications such as electrical cars or storage devices for solar energy. A patent has been filed and hopefully the technology can become available shortly.

Jan Rabaey’s roadmap to low power design

December 5, 2007

     Professor Jan Rabaey of UC Berkeley gave the keynote address, on “Scaling the Power Wall, Revisiting Low-Power Design Rules.” at the International Symposium on System-on-Chip in Tampere, Finland. He noted that power consumption has been addressed as an issue in the past and that there were two proposed solutions to the problem. Allowing power-supply voltage to be a design variable, and to use new low power design techniques. Supply voltages have been dramatically reduced and most designs go below 1V. However, Rabaey suggest that we made spotty progress in using new low power techniques such as matching computation to architecture, preserving data locality, exploiting signal statistics and supplying energy on demand. Instead of matching computation to architecture, most chip designers fit computation problems to fixed architectures. There is inappropriate use of global data buses to move data around on the chip. There has not been any exploitation of signal statistics. The most used technique has been supplying energy to circuits on demand, mostly through clock gating. This technique has succeeded because of the availability of automated EDA tools that can do this job. The rest of the new design techniques require mental intervention and are not automated, hence their lack of adoption. Moreover, we have missed the importance of standby power. Supply voltages now approach transistor threshold voltages and as a result, large numbers of leaky transistors inhabit big nanometer chip designs.
     There is some good news; EDA companies are starting to form a low-power design methodology. This is driven by the fact that power is now the dominant design constraint. For example, data center costs for Web-centric companies such as Google are now dominated not by equipment or by plant costs but by energy costs. At the small end of the design spectrum, mobile devices are now completely defined by their available power budgets. In the past Technology scaling was a solution but according to Rabaey it will no longer help. This is because of silicon’s fundamental limits. Although active power density continues to be somewhat limiting, leakage power, which is growing at the same rate as computational power, is the killer. At the same time, technology scaling is actually causing more design pain—in the form of process variability, which drives chip designers to adopt wider design margins or face lower manufacturing yields. Smaller circuits are also subject to more soft errors from many causes.
     Rabaey suggests the following techniques for a successful electronic design:

  • Concurrency galore
  • Always-optimal design (no energy waste, ever)
  • Better-than-worst-case design (accommodate computational and memory failures)
  • Ultra-low supply voltages
  • “Exploration of the unknown”

Concurrency is a good idea because it drives clock rates down, which can help save energy by allowing a further reduction of supply voltage. Always-optimal design attempts to optimize at design time, during run time, and during sleep modes. This approach requires additional circuitry. Better-than-worst-case design (also called aggressive deployment) moves design from the use of “design corners,” essentially worst-case design, to one where circuits operate in statistical operating regions where some errors are tolerated. This design approach requires the use of error-detection and –correction circuits. Ultra-low-voltage design recognizes that the true operating limit for a MOSFET is actually about 35 mV. Rabaey suggests that we can more closely approach this limit by rethinking all of digital logic. He suggested stacked transistors and logic design based on transmission gates as likely areas for productive research. Exploring the unknown employs radically new architectures that might employ millions of small processors on a chip, arrayed in collaborative networks. Experiments with search and recognition algorithms suggest that such imprecise networks of estimating processors might produce excellent results with very low energy consumption.


Wireless Power

November 27, 2007

Broadcasting power through RF and using it to power electronic devices is not a new idea. This concept has been around for a long time, for example at the St. Louis World’s Fair in 1904 a prize was offered for a successful attempt to power a 75 W motor by energy transferred through space at a distance of 30m. However, for both technical and health reasons, wireless power transfer technologies have not yet made a stand in consumer electronics.  Focused beams of radiation are definitely a health safety risk, and energy bouncing of walls at different frequencies and voltage levels is difficult to capture as a steady voltage source. However, for low power applications there is hope. There are a few companies that have developed technologies that transmit power at safe levels making it possible to transfer energy to low power devices wirelessly. There are still major limitations to the technology. For instance, the distances that energy can be sent is limited to only about a meter and the amount of energy that can be transferred is limited to levels that can be used to recharge nothing bigger than a cell phone battery. But with electronics becoming less power hungry this could all change. Check out some of the start-up companies that are actively pushing the limits of this technology.